The present disclosure relates to semiconductor devices including through electrodes, and methods of manufacturing the devices.
In recent years, for higher integration of semiconductor devices and integration of various types of semiconductor devices, stacked semiconductor devices formed by stacking a plurality of semiconductor chips in a package have been developed. In most of them, the semiconductor devices to be stacked are electrically connected by wire bonding with a relay substrate such as an interposer interposed between the semiconductor devices. In this structure, since drawn-around wiring for connecting the semiconductor chips is long, parasitic capacitance in the wiring increases with an increase in wiring resistance. This increases an RC delay to limit high-speed operation. In addition, since the area for drawing around the wires increases the size of the entire semiconductor device, miniaturization and reduction in the height of the device have been also limited.
A method of connecting semiconductor devices to be stacked using through electrodes formed by filling through-holes formed in semiconductor devices with metal or conductive resin is known as a solution. (See, for example, Japanese Patent Publication No. 2003-309221). With this structure, the semiconductor devices to be stacked can be connected at the minimum distance, and thus, the interconnection length can be reduced as compared to connection by wire bonding, thereby reducing interconnection resistance and parasitic capacitance. As a result, RC delays are reduced to enable high-speed operation. In addition, since the region for drawing around the wires is not required, only the sizes of the semiconductor devices to be stacked themselves determine the size of the entire stacked semiconductor device. Moreover, the thicknesses of the semiconductor devices to be stacked are reduced, thereby reducing the height of the staked semiconductor device, and thus, the size of the entire semiconductor device can be reduced as compared to the conventional structure.
FIG. 13 is a cross-sectional view of a conventional semiconductor device including a through electrode. As shown in FIG. 13, in a conventional semiconductor device 200, a through-hole 211 is formed in a semiconductor substrate 210 having a first surface 210a which is an integrated circuit formation surface, and a second surface 210b which is opposite to the first surface 210a. The through-hole 211 extends from the first surface 210a to the second surface 210b. An interlayer insulating film 212 including an interconnect layer 213 is formed on the first surface 210a. The through-hole 211 is also formed in the interlayer insulating film 212 to reach the interconnect layer 213. An insulating film 214 is formed on the inner walls of the through-hole 211 and on the second surface 210b. A barrier film 215 is formed on the inner walls of the through-hole 211 with the insulating film 214 interposed therebetween. A conductive portion 216, which serves as a through electrode, is formed to fill the through-hole 211 provided with the insulating film 214 and the barrier film 215. The insulating film 214 electrically insulates the semiconductor substrate 210 from the conductive portion 216. The barrier film 215 reduces diffusion of a conductive material forming the conductive portion 216 into the semiconductor substrate 210.
A method of manufacturing the semiconductor device 200 shown in FIG. 13 will be described below.
First, after forming an integrated circuit etc. (not shown) on the first surface 210a of the semiconductor substrate 210, the interlayer insulating film 212, which includes the interconnect layer 213 electrically connected to the integrated circuit, is formed on the first surface 210a. Then, the back surface (i.e., the surface opposite to the first surface 210a) of the semiconductor substrate 210 is mechanically polished/ground or chemically polished/ground to reduce the thickness of the semiconductor substrate 210. After that, the through-hole 211 is formed from the second surface 210b, which is a new surface of the back surface of the semiconductor substrate 210, to expose the interconnect layer 213 inside the through-hole 211. Next, after forming the insulating film 214 on the inner walls of the through-hole 211 and on the second surface 210b, the barrier film 215 is formed on the inner walls of the through-hole 211 with the insulating film 214 interposed therebetween. Then, the through-hole 211 provided with the insulating film 214 and the barrier film 215 is filled with the metal material to form the conductive portion 216, which serves as a through electrode.